JTAG

JTAG = Joint Test Action Group

JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) pinout

[1]

Pinout (10 pin)

File:Idc10m.png

10 PIN IDC MALE at the CPU.

File:Idc10f.png

10 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Dir	Description
1	TCK		Test Clock
2	GND		Ground
3	TDO		Test Data Output
4	VTref
5	TMS		Test Mode Select
6	nSRST		System Reset
7	Vsupply
8	NC		Not connected
9	TDI		Test Data Input
10	GND		Ground

Note: Direction is target (CPU) relative JTAG-bus (PC)

Pinout (12 pin)

12 PIN IDC 2x6 0.05" MALE at the CPU.

12 PIN IDC 2x6 0.05" FEMALE at the cable/programmer.

Pin	Name	Dir	Description
1	nTRST		JTAG Reset
2	GND		Ground
3	TDI		Test Data Input
4	GND		Ground
5	TDO		Test Data Output
6	GND		Ground
7	TMS		Test Mode Select
8	GND		Ground
9	TCK		Test Clock
10	GND		Ground
11	nSRST		System Reset
12	GND		Ground

MAJIC® Interface Specs for ARM Debug Interface and Intel XScale® Technology

Pinout (14 pin TX)

Used by Texas Instruments.

File:Idc14m.png

14 PIN IDC MALE at the CPU.

File:Idc14f.png

14 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Dir	Description
1	TMS		Test Mode Select
2	nTRST		TAP reset
3	TDI		Test Data Input
4	GND		Ground
5	VCC		Power
6	n/c		Ground
7	TDO		Test Data Output
8	GND		Ground
9	RTCK		Test Clock?
10	GND		Ground
11	TCK		Test Clock
12	GND		Ground
13	nEMU0
14	nEMU1

Pinout (14 pin ARM)

File:Idc14m.png

14 PIN IDC MALE at the CPU.

File:Idc14f.png

14 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Dir	Description
1	VCC
2	GND		Ground
3	nTRST
4	GND		Ground
5	TDI		Test Data Input
6	GND		Ground
7	TMS		Test Mode Select
8	GND		Ground
9	TCK		Test Clock
10	GND		Ground
11	TDO		Test Data Output
12	nSRST		Ground
13	VCC
14	GND		Ground

Pinout (20 pin ARM)

Used for ARM processors.

20 PIN IDC MALE at the CPU.

20 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Dir	Description
1	VTref
2	GND or VSupply		Ground or VSupply
3	nTRST
4	GND		Ground
5	TDI		Test Data Input
6	GND		Ground
7	TMS		Test Mode Select
8	GND		Ground
9	TCK		Test Clock
10	GND		Ground
11	RTCK
12	GND		Ground
13	TDO		Test Data Output
14	GND		Ground
15	nSRST
16	GND		Ground
17	DBGRQ
18	GND		Ground
19	DBGACK
20	GND		Ground

Technical description

TDI

TDI = Test Data In

TDO

TDO = Test Data Out

TCK

TCK = Test Clock

TMS

TMS = Test Mode Select

TRST

TRST = Test ReSeT
Optional.

Links

• Corelis: Boundary-Scan Tutorial

Standards

• IEEE 1149.1-1990: Test Access Port and Boundary-Scan Architecture
• IEEE 1149.1-1994b: Supplement to IEEE Std 1149.1-1990 (Boundary-Scan Description Language, BSDL)

See also

• EJTAG

Source

• Ethernut 3 JTAG info
• http://wiki.openwrt.org/OpenWrtDocs/Customizing/Hardware/JTAG_Cable
• http://www.nohau.com/appnotes/arm_connections.pdf

Contributions

• Joakim Ögren