From HwB

EISA=Extended Industry Standard Architecture

Developed by Compaq, AST, Zenith, Tandy...



|            (component side)                 |
|                                             |
|___________ ISA-16bit __       ISA-8bit    __|
            |||||||||||  |||||||||||||||||||  A1(front)/B1(back)
             | | | | |    | | | | | | | | |  EISA: E1(front)/F1(back)

A,C,E,G=Component Side A,B,F,H=Sold Side

Notdrawn.png computer)

62+38 PIN EDGE CONNECTOR at the computer.

Pin Name Description
E1 CMD# Command Phase
E2 START# Start Phase
E4 EX32# EISA Slave Size 32
E5 GND Ground
E6 KEY Access Key
E7 EX16# EISA Slave Size 16
E8 SLBURST# Slave Burst
E9 MSBURST# Master Burst
E10 W/R# Write/Read
E11 GND Ground
E12 RES Reserved
E13 RES Reserved
E14 RES Reserved
E15 GND Ground
E16 KEY Access Key
E17 BE1# Byte Enable 1
E18 LA31# Latchable Addressline 31
E19 GND Ground
E20 LA30# Latchable Addressline 30
E21 LA28# Latchable Addressline 28
E22 LA27# Latchable Addressline 27
E23 LA25# Latchable Addressline 25
E24 GND Ground
E25 KEY Access Key
E26 LA15 Latchable Addressline 15
E27 LA13 Latchable Addressline 13
E28 LA12 Latchable Addressline 12
E29 LA11 Latchable Addressline 11
E30 GND Ground
E31 LA9 Latchable Addressline 9
F1 GND Ground
F2 +5V +5 VDC
F3 +5V +5 VDC
F4 ---
F5 ---
F6 KEY Access Key
F7 ---
F8 ---
F9 +12V +12 VDC
F10 M/IO# Memory/Input-Output
F11 LOCK# Lock bus
F12 RES Reserved
F13 GND Ground
F14 RES Reserved
F15 BE3# Byte Enable 3
F16 KEY Access Key
F17 BE2# Byte Enable 2
F18 BE0# Byte Enable 0
F19 GND Ground
F20 +5V +5 VDC
F21 LA29# Latchable Addressline 29
F22 GND Ground
F23 LA26# Latchable Addressline 26
F24 LA24# Latchable Addressline 24
F25 KEY Access Key
F26 LA16 Latchable Addressline 16
F27 LA14 Latchable Addressline 14
F28 +5V +5 VDC
F29 +5V +5 VDC
F30 GND Ground
F31 LA10 Latchable Addressline 10
G1 LA7 Latchable Addressline 7
G2 GND Ground
G3 LA4 Latchable Addressline 4
G4 LA3 Latchable Addressline 3
G5 GND Ground
G6 KEY Access Key
G7 D17 Data 17
G8 D19 Data 19
G9 D20 Data 20
G10 D22 Data 22
G11 GND Ground
G12 D25 Data 25
G13 D26 Data 26
G14 D28 Data 28
G15 KEY Access Key
G16 GND Ground
G17 D30 Data 30
G18 D31 Data 31
G19 MREQx Master Request
H1 LA8 Latchable Addressline 8
H2 LA6 Latchable Addressline 6
H3 LA5 Latchable Addressline 5
H4 +5V +5 VDC
H5 LA2 Latchable Addressline 2
H6 KEY Access Key
H7 D16 Data 16
H8 D18 Data 18
H9 GND Ground
H10 D21 Data 21
H11 D23 Data 23
H12 D24 Data 24
H13 GND Ground
H14 D27 Data 27
H15 KEY Access Key
H16 D29 Data 29
H17 +5V +5 VDC
H18 +5V +5 VDC
H19 MAKx Master Acknowledge


This section is currently based solely on the work by Mark Sokos.

This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and amateurs can design their own EISA compatible cards.

It is not intended to provide complete coverage of the EISA standard.

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connect with the EISA signals.

Signal Descriptions

+5, -5, +12, -12

Power supplies. -5 is often not implemented.


Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer.


Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE.


Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher.


Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.


Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the CPU.


Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers.


Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle.


System Data lines. They are bi-directional and tri-state.


DMA Acknowledge.


DMA Request.


EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers.


EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers.


EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states.


I/O size 16. Generated by a 16 bit slave when addressed by a bus master.


I/O Read Command line.


I/O Write Command line.


Interrupt Request. IRQ2 has the highest priority.


Latchable Address lines.


Asserting this signal prevents other bus masters from requesting control of the bus.


Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.


16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.


Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation.


Memory Access, 16 bit


Memory Read Command line.


Master Request for Slot x: This is a slot specific request for the device to become the bus master.


Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles.


Memory Write Command line.


No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.


Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.


Refresh. Generated when the refresh logic is bus master.


This signal goes low when the machine is powered up. Driving it low will force a system reset.


System Address Lines, tri-state.


System Bus High Enable, tri-state. Indicates a 16 bit data transfer.


Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles.


Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.


Standard Memory Write Command line. Indicates a memory write in the lower 1 MB area.


Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD).


Terminal Count. Notifies the CPU that that the last DMA data transfer operation is complete.


Write or Read. Used to indicate if the current bus cycle is a read or a write operation.