AM-100 bus

From HwB

Alpha Micro made a version of S-100 bus for 16-bit processor.

Pinout

1     (Component side)      50
==============================
100     (Solder side)       51

Pin	Name	Type	Dir	Description
1	+8 V	Power		+8 Volts
2	+18 V	Power		+18 Volts
3	----	Fr panel		External Ready To Processor
4	/VI0	Control		Vector Interrupt Line 0
5	/VI1	Control		Vector Interrupt Line 1
6	/VI2	Control		Vector Interrupt Line 2
7	/VI3	Control		Vector Interrupt Line 3
8	/VI4	Control		Vector Interrupt Line 4
9	/VI5	Control		Vector Interrupt Line 5
10	/VI6	Control		Vector Interrupt Line 6
11	/VI7	Control		Vector Interrupt Line 7
12
13
14
15
16
17
18	----
19	----
20	???
21	---
22	---
23	---
24	phi2	Clock		Primary Processor Clock Line
25	/PSTVAL		?	?
26	PHLDA	Control		Processor In Hold Condition
27	PWAIT	Control		Processor In Wait Condition
28	PINTE	Control		Processor Permits Interrupts When Active
29	A5	Address		Address Line 5
30	A4	Address		Address Line 4
31	A3	Address		Address Line 3
32	A15	Address		Address Line 15
33	A12	Address		Address Line 12
34	A9	Address		Address Line 9
35	DO1	Data		Data Output Line 1
36	DO0	Data		Data Output Line 0
37	A10	Address		Address Line 10
38	DO4	Data		Data Output Line 4
39	DO5	Data		Data Output Line 5
40	DO6	Data		Data Output Line 6
41	DI2	Data		Data Input Line 2
42	DI3	Data		Data Input Line 3
43	DI7	Data		Data Input Line 7
44	SM1	State		Processor Instruction Fetch Signal
45	SOUT	State		Processor I/O Write Signal
46	SINP	State		Processor I/O Read Signal
47	SMEMR	State		Processor Memory Read Signal
48
49	CLOC	Clock		2Mhz Clock Signal
50	GND	Power		Logical And Power Ground
51	+8V	Power		+8 Volts
52	-16V	Power		-18 Volts
53	???
54	???
55	???
56	/DMAGR7
57	/DMAGR6
58	/DMAGR5
59	/DMAGR4
60	/DMAGR3
61	/DMAGR2
62	/DMAGR1
63	/DMAGR0
64	/DMARCVD
65	---
66	---
67	???
68	MWRT	Ctrl/frp		Memory Write From Processor Or Front Panel
69	???
70	???
71	???
72	???
73	???
74	/DMAREQ		?	DMA Request
75	/PRESET	Control		Forces Processor To Reset State
76	???
77	/PWR	Control		Active When Processor Writes (I/O Or Memory)
78	PDBIN	Control		Active When Processor Reads (I/O Or Memory)
79	A0	Address		Address Line 0
80	A1	Address		Address Line 1
81	A2	Address		Address Line 2
82	A6	Address		Address Line 6
83	A7	Address		Address Line 7
84	A8	Address		Address Line 8
85	A13	Address		Address Line 13
86	A14	Address		Address Line 14
87	A11	Address		Address Line 11
88	DO2	Data		Data Output Line 2
89	DO3	Data		Data Output Line 3
90	DO7	Data		Data Output Line 7
91	DI4	Data		Data Input Line 4
92	DI5	Data		Data Input Line 5
93	DI6	Data		Data Input Line 6
94	DI1	Data		Data Input Line 1
95	DI0	Data		Data Input Line 0
96	SINTA	Control		Acknowledge Signal For Pint Request
97	/SWO	Control		Processor In Write Status
98	???
99	/POC	Ft panel		Power-On Clear Signal
100	GND			Power And Signal Ground