240 pin FBDIMM DDR2

From HwB

240 pin FBDIMM DDR2
  • ECC
  • Single/Dual Rank

Contents

Pinout

Notdrawn.png

Front

Pin Name
1 VDD
2 VDD
3 VDD
4 VSS
5 VDD
6 VDD
7 VDD
8 VSS
9 VCC
10 VCC
11 VSS
12 VCC
13 VCC
14 VSS
15 VTT
16 VID1
17 RESET#
18 VSS
19 RFU2
20 RFU2
21 VSS
22 PN0
23 PN0#
24 VSS
25 PN1
26 PN1#
27 VSS
28 PN2
29 PN2#
30 VSS
31 PN3
32 PN3#
33 VSS
34 PN4
35 PN4#
36 VSS
37 PN5
38 PN5#
39 VSS
40 PN13
41 PN13#
42 VSS
43 VSS
44 RFU
45 RFU
46 VSS
47 VSS
48 PN12
49 PN12#
50 VSS
51 PN6
52 PN6#
53 VSS
54 PN7
55 PN7#
56 VSS
57 PN8
58 PN8#
59 VSS
60 PN9
61 PN9#
62 VSS
63 PN10
64 PN10#
65 VSS
66 PN11
67 PN11#
68 VSS
69 VSS
70 PS0
71 PS0#
72 VSS
73 PS1
74 PS1#
75 VSS
76 PS2
77 PS2#
78 VSS
79 PS3
80 PS3#
81 VSS
82 PS4
83 PS4#
84 VSS
85 VSS
86 RFU1
87 RFU1
88 VSS
89 VSS
90 PS9
91 PS9#
92 VSS
93 PS5
94 PS5#
95 VSS
96 PS6
97 PS6#
98 VSS
99 PS7
100 PS7#
101 VSS
102 PS8
103 PS8#
104 VSS
105 RFU2
106 RFU2
107 VSS
108 VDD
109 VDD
110 VSS
111 VDD
112 VDD
113 VDD
114 VSS
115 VDD
116 VDD
117 VTT
118 SA2
119 SDA
120 SCL

Back

Pin Name
121 VDD
122 VDD
123 VDD
124 VSS
125 VDD
126 VDD
127 VDD
128 VSS
129 VCC
130 VCC
131 VSS
132 VCC
133 VCC
134 VSS
135 VTT
136 VID0
137 DNU/M_TEST
138 VSS
139 RFU2
140 RFU2
141 VSS
142 SN0
143 SN0#
144 VSS
145 SN1
146 SN1#
147 VSS
148 SN2
149 SN2#
150 VSS
151 SN3
152 SN3#
153 VSS
154 SN4
155 SN4#
156 VSS
157 SN5
158 SN5#
159 VSS
160 SN13
161 SN13#
162 VSS
163 VSS
164 RFU1
165 RFU1
166 VSS
167 VSS
168 SN12
169 SN12#
170 VSS
171 SN6
172 SN6#
173 VSS
174 SN7
175 SN7#
176 VSS
177 SN8
178 SN8#
179 VSS
180 SN9
181 SN9#
182 VSS
183 SN10
184 SN10#
185 VSS
186 SN11
187 SN11#
188 VSS
189 VSS
190 SS0
191 SS0#
192 VSS
193 SS1
194 SS1#
195 VSS
196 SS2
197 SS2#
198 VSS
199 SS3
200 SS3#
201 VSS
202 SS4
203 SS4#
204 VSS
205 VSS
206 RFU1
207 RFU1
208 VSS
209 VSS
210 SS9
211 SS9#
212 VSS
213 SS5
214 SS5#
215 VSS
216 SS6
217 SS6#
218 VSS
219 SS7
220 SS7#
221 VSS
222 SS8
223 SS8#
224 VSS
225 RFU2
226 RFU2
227 VSS
228 SCK
229 SCK#
230 VSS
231 VDD
232 VDD
233 VDD
234 VSS
235 VDD
236 VDD
237 VTT
238 VDDSPD
239 SA0
240 SA1

Notes:

  • 1. These pin positions are reserved for forwarded clocks to be used in future module implementations
  • 2. These pin positions are reserved for future architecture flexibility
  • 3. The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, SS9/SS9#
  • 4. RFU = Reserved Future Use

Contributors

Source

Retrieved from "http://www.hardwarebook.info/index.php?title=240_pin_FBDIMM_DDR2&oldid=8320"